1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to the semiconductor memory device having a memory cell array provided with a plurality of memory cells mounted in a matrix form and having a plurality of banks composed of circuits mounted around the memory cell array.
2. Description of the Related Art
As is well known, a DRAM (Dynamic Random Access Memory), one type of semiconductor memory device, is constructed of memory cell arrays in which memory cells each being composed of a MOS (Metal Oxide Semiconductor) transistor for switching (hereinafter referred to as a "switching transistor") and of a memory capacitor are arranged in a matrix form. The memory capacitor is adapted to store one-bit data showing a "0" or "1" state depending on whether an electric charge is accumulated or not therein. A source electrode of the switching transistor constituting the memory cell is connected to one electrode of the memory capacitor. A gate electrode of the switching transistor is connected to a word line installed in parallel to a row. A drain electrode of the switching transistor is connected to a bit line installed in parallel to a column.
For example, when data stored in a certain memory cell is read out, it is necessary to activate a corresponding word line, i.e., to turn ON the switching transistor constituting the memory cell by applying an "H" (high) level voltage through the word line. This enables a detection of a rise or drop in voltages occurring on a corresponding bit line caused by an electric charge accumulated in the memory capacitor and the reading of one-bit data showing a "0" or "1" state.
On another hand, when data composed of the "1" state is written in a memory cell, for example, the electrical charge is accumulated in the above memory capacitor by activating the corresponding word line, i.e., by applying the "H" level voltage to the word line to turn the switching transistor ON and, at a same time, after the memory capacitor is charged by applying the "H" level voltage to the corresponding bit line, the switching transistor is turned OFF by applying a "L" (low) level voltage to the word line. Though the electrical charge accumulated in the memory capacitor is borne once therein, due to a minimal amount of leakage current, it decreases gradually as time elapses and is lost. It is, therefore, necessary to perform an operation called a "refresh" in which, after the switching transistor is turned ON every certain period of time, the electric charge being stored but gradually decreasing in the memory capacitor is detected and the detected charge is amplified by a sense amplifier, and then the same memory capacitor is again charged.
If the DRAM has several megabit capabilities, one memory cell array is sufficient. However, if it has several tens of megabits to several gigabit capabilities, a number of memory cells becomes several tens of thousands to several tens of billions, which causes inconveniences of processing enormous numbers of word lines and bit lines, longer access time for writing or reading data in and from a desired memory cell, or the like. To avoid this problem, the DRAM is ordinarily provided with a plurality of memory cell arrays. A part of the memory cell combined with a circuit mounted around the memory cell is called a "bank". In the DRAM having a plurality of banks, the refreshing operation described above is performed using a counter called a "refresh counter" internally mounted by the following procedures. That is, in the DRAM having two banks, for example, a counter value of the refresh counter is renewed and two banks are alternately selected by least significant several bits. Then, in a selected bank, "H" level voltages are applied, in order, to a plurality of word lines based on the counter value and all switching transistors connected to the word lines are turned ON and, after the electric charge is produced by the switching transistors being in an ON state, the stored but gradually decreasing charge in the memory capacitor is amplified by the sense amplifier and the same memory capacitor is again charged.
In the above-described DRAM having the plurality of banks, a refresh counter test for checking whether the above refresh counter is operating normally or not is introduced as one of functions contained in specifications of the DRAM. In the refresh counter test, whether the refresh counter is operating normally or not is confirmed by writing, in order, specified data into each of the memory cells while data stored in all or a part of the memory cells is being refreshed, then by reading, in order, data written in each of the memory cells after completion of the refreshing operation and by checking if data written previously in each of the memory cells is correctly read. In this test, the ordinary refresh in which, as described above, the electric charge stored but gradually decreasing in the memory capacitor is amplified and then the same memory capacitor is again charged, is not used. The ordinary refresh is generally called "automatic refresh" or "self refresh" in which, once a command to execute the refreshing operation is entered from outside, the refreshing operation does not stop until the amplification of the charge stored but gradually decreasing in the memory capacitor is ended and until a stop command is executed.
In contrast, the refresh used in the refresh counter test is generally called a "CBR (Cas Before Ras) refresh", in which, every time the command to execute the refresh is entered from outside, the counter value of the refresh counter is sequentially incremented to execute the refreshing operation.
A brief explanation of the refresh counter test is given below by referring to FIG. 14 and by using, as an example, a synchronous DRAM which is provided with banks A and B and a supplied command in synchronization with a clock from a CPU (Central Processing Unit), memory control unit or a like mounted externally and operates based on the supplied command.
First, in response to a mode register set command MRS (see (2) in FIG. 14) entered from outside in synchronization with the clock CLK (see (1) in FIG. 14), contents stored in the mode register are changed to an operation code used to designate a refresh counter test mode obtained by decoding an address supplied from outside. A plurality of mode registers mounted around the bank is used to temporarily store a variety of information including a burst length showing a number of clocks in a burst mode to perform consecutive operations of writing and reading data the like operations and various operation codes used to designate the refresh counter test mode and the burst mode.
Next, in response to a refresh command REF (see (2) in FIG. 14) supplied from outside in synchronization with the clock CLK (see (1) in FIG. 14), the counter value of the refresh counter is renewed. If a least significant bit RCL (see (7) in FIG. 14) of the counter value is, for example, a value RCLB to be used for activating the bank B, a signal RASB (see (6) in FIG. 14) is produced, based on the value RCLB, which activates a row decoder mounted corresponding to the bank B for applying the "H" level signal to a specified word line of the bank B by decoding an external row address supplied from outside or an internal row address composed of the counter value of the refresh counter. Therefore, since the row decoder corresponding to the bank B is activated by the signal RASB, the "H" level voltage is applied to the word line of the bank B designated by the row address and the refreshing is performed on the memory cell connected to the word line.
Then, in order to write specified data in the bank which has already been refreshed, it is necessary to designate the bank into which data is to be written and to activate a column switch which is a switch used to connect the bit line installed corresponding to the bank with an input/output line, installed in parallel to the bit line, adapted to input and/or output data fed from the outside of the semiconductor memory device into or from the memory cell, i.e., to activate a column decoder for applying the "H" level voltage. The designation of the bank to be refreshed is performed by activating the row decoder corresponding to the bank A or B in accordance with a signal RASA or RASB (see (5) and (6) in FIG. 14) produced based on the least significant bit RCL of the counter value of the refresh counter mounted in the semiconductor memory device. On the other hand, the designation of the bank performed when data is written after being refreshed is ordinarily carried out by activating the column decoder corresponding to the bank A or B in accordance with a signal CASA or CASB produced based on the most significant several bits of the address fed from outside. In this case, however, since the counter value of the refresh counter cannot be recognized from outside, it is impossible to realize, from outside, which bank, A or B, has already been refreshed.
If there is, therefore, nonconformity between the bank (the bank B in the present case) designated based on the signal RASB (see (6) in FIG. 14) produced in accordance with the least significant bit RCL (the value RCLB in the present case) of the counter value of the refresh counter counted up by the refresh command and the bank (the bank A in the present case) designated based on the signal CASA (see (3) in FIG. 14) based on the most significant several bits of the address fed from outside together with the write command entered following the refresh command, it is impossible to write specified data into the bank which has already been refreshed. Such an inconvenience occurs at a time of reading data alike. When this type of event occurs, normal execution of the refresh counter test is impossible accordingly.
A semiconductor memory device designed to overcome this shortcoming is disclosed, for example, in Japanese Laid-open Patent Application No. Hei10-92175. FIG. 15 is a schematic block diagram showing electrical configurations of a signal generating circuit of a conventional semiconductor memory device disclosed in the above application. The signal generating circuit is chiefly composed of OR gates 1 and 2, inverters 3 and 4, a register 5, switches 6, 7 and 8 and flip-flops 9 and 10. The OR gate 1 is adapted to feed an output signal obtained by ORing a burst write command BWR, fed from outside, to write data in the burst mode with a burst read command BRD, fed from outside, to read data in a burst mode, to each of first input terminals IN.sub.1 of the flip-flops 9 and 10. The OR gate 2 is adapted to feed an output signal obtained by ORing a burst stop command BST, fed from outside, to stop the burst mode with a burst length end command BLE, fed from outside, to instruct the burst mode to be automatically terminated after a length of the data for writing and reading has reached a predetermined burst length, to each of second input terminals IN.sub.2 of the flip-flops 9 and 10.
The inverter 3 is operated to invert a test mode signal TM which is produced in accordance with a refresh counter test command supplied from outside and goes high during the execution of the refresh counter test and to feed an inverted test mode signal TM to a control terminal of the switch 7.
The switch 6 is turned ON/OFF in accordance with a refresh command REF supplied from outside and is adapted to feed the least significant bit RCL of the counter value of the refresh counter to the register 5. The register 5 is composed of two inverters and, after temporarily holding the least significant bit RCL of the counter value of the refresh counter fed through the switch 6, feeds it to an input terminal of the inverter 4. The inverter 4 is used to invert an output signal from the register 5 and to feed it to an input terminal of the switch 8. The switch 7 is turned ON/OFF in accordance with an output signal from the inverter 3 and feeds the most significant bit EAM of an address supplied from outside to each of the third input terminals IN.sub.3 of the flip-flops 9 and 10. The switch 8 is turned ON/OFF in accordance with the test mode signal TM and feeds an output signal of the inverter 4 to each of third input terminals IN.sub.3 of the flip-flops 9 and 10. The flip-flops 9 and 10, when activated by a signal fed to their third input terminals IN.sub.3, are operated to output a signal CASA which changes from its "L" level to its "H" level in accordance with the output signal from the OR gate 1, i.e., the burst write command BWR or the burst read command BRD and a signal CASB which changes from its "H" level to its "L" level in accordance with the output signal from the OR gate 2, i.e., the burst stop command BST or burst length end command BLE.
Next, operations of the semiconductor memory device having configurations described above will be described below.
First, at a time of ordinary refreshing operation and at a time of writing or reading, since the test mode signal TM is not supplied, the switch 7 is turned ON and the switch 8 is turned OFF. This causes the most significant bit EAM of an address supplied from outside to be fed to each of third input terminals IN.sub.3 of the flip-flops 9 and 10 and therefore the flip-flop 9 or 10 is activated in accordance with the most significant bit EAM of the address, and the signal CASA or CASB is outputted.
In contrast, at a time of executing the refresh counter test, since the test mode signal TM is supplied, the switch 8 is turned ON and the switch 7 is turned OFF. When the refresh command REF is supplied, the switch 6 is turned ON. Since the least significant bit RCL of the counter value of the refresh counter is fed through the switch 6, register 5, inverter 4 and switch 8 to each of the third input terminals IN.sub.3 of the flip-flops 9 and 10, the flip-flop 9 or flip-flop 10 is activated in accordance with the least significant bit RCL of the counter value of the refresh counter and the signal CASA or CASB is outputted.
By configuring as above, at the time of executing the refresh counter test, since a signal to activate the column decoder as well as a signal to activate the row decoder is produced from the least significant bit RCL of the counter value of the refresh counter counted up in accordance with the refresh command REF, the bank designated for the refresh conforms, without fail, to the bank designated for writing or reading data after the refreshing operation is performed. This enables the normal execution of the refresh counter test.
However, the conventional semiconductor memory device provided with the function of the refresh counter test contained in its specifications has problems. That is, complicated signal generating circuits are required for providing the function for the refresh counter test, which occupies large areas on a chip of the conventional semiconductor memory device. Moreover, signal lines required to transmit the least significant bit RCL of the counter value of the refresh counter must be installed on an overall area of the chip. Thus, the chip area is reduced by the above complicated circuits, wiring or like, causing the impedance of high integration of the semiconductor memory device.